POWER ELECTRONICS QUIZ

 Positive source signal.

  Positive gate signal.

 Positive drain signal.

 None of these.

 60 KHz.

  100 KHz.

 10 KHz.

 5 KHz.

  gate signal must be removed.

None of these

 gate signal should present but can be removed.

 gate signal is always present.

 series connection.

 both B and C.

 anti parallel connection.

  parallel connection.

 to limit dV / dt of SCR.

 to limit di / dt of SCR.

 for voltage equalisation.

  both B and C.

 Rise time.

 Delay time.

 Same for every case.

  Spread time.

A four-terminal device

Like a bidirectional SCR

Not a thyristor

None of these

  junction J2 is in reverse bias and J1, J3 is in forward bias.

  Junction J1 and J2 is in forward bias and J3 is in reverse bias.

  Junction J1, J3 is in reverse bias and J2 is in forward bias.

  junction J3 is in forward bias and J1, J2 is in reverse bias.

 Low dv/dt.

 High dv/dt.

  High di/dt.

 Low di/dt.

 RLC underdamped.

 RL.

 RLC overdamped.

 RLC critically damped.