An I/O processor controls the flow of information between Two I/O devices Cache and main memory Cache memory and I/O devices Main memory and I/O devices TRUE ANSWER : ? YOUR ANSWER : ?
After RESET 8255 will be in unchanged condition mode 0; all ports are input mode 0; all ports are output mode 2 TRUE ANSWER : ? YOUR ANSWER : ?
Identify the non-programmable interfacing device from the following 8295. 8255. 8257. 8212. TRUE ANSWER : ? YOUR ANSWER : ?
Which of the following conditions is not allowed in an RS latch? R is negated, S is asserted R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted TRUE ANSWER : ? YOUR ANSWER : ?
When any data transfer instruction, to transfer the data from memory to microprocessor, is executed the condition flags are always set affected indicating specific conditions always reset not affected TRUE ANSWER : ? YOUR ANSWER : ?
FPGA means Forward Parallel Gate Array Forward Programmable Gate Array Field Parallel Gate Array Field Programmable Gate Array TRUE ANSWER : ? YOUR ANSWER : ?
Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran. Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran. Both A and R are correct and R is correct explanation of A A is wrong R is correct A is correct R is wrong Both A and R are correct but R is not correct explanation of A TRUE ANSWER : ? YOUR ANSWER : ?
________is the only non-vectored interrupt in 8085 microprocessor. RST 5.5 TRAP RST 7 INTR TRUE ANSWER : ? YOUR ANSWER : ?