MICROPROCESSOR QUIZ

 may be in RAM or ROM

 resides in ROM

 resides in RAM

 resides in microprocessor

 A fetch cycle

 An I/O read cycle

 A memory read cycle

 A memory write cycle

 mode 0; all ports are input

 mode 0; all ports are output

 mode 2

 unchanged condition

 AND that bit with “1” and remaining bits with “0”.

 AND that bit with “0” and remaining bits with “1”.

 OR that bit with “1” and remaining bits with “0”.

 OR that bit with “0” and remaining bits with “1”.

 direct memory access for the user

None of these

 direct memory access for the I/O device

 direct memory access for microprocessor

 None of these

 Bus Interface Unit (BIU)

 Both ‘b’ and ‘c’

 Execution Unit (EU)

 all bits set (i.e. FFH)

 same as the content of A7-A0

 all bits reset (i.e. 00H)

 irrelevant

 sets zero and sign flags

 sets zero and carry flags

 reset zero and parity flags

 reset carry and sign flags

None of these

Integer part, fraction part along with positive or negative sign

Integer part

Integer part and fraction part

 To achieve all the functions listed above

 Enable the data bus to be used as low order address bus

 To latch data D0-D7 from data bus

 To disable data bus