Digital Electronics In an SR latch built from NOR gates, which condition is not allowed S=0, R=1 S=0, R=0 S=1, R=0 S=1, R=1 S=0, R=1 S=0, R=0 S=1, R=0 S=1, R=1 ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics The AND-OR realization of a combinational circuit requires three 3-input AND gates and one 3-input OR gate. This circuit can be designed using three 3-input OR gates and one 3-input AND gate None of these four input NAND gates only three 3-input NAND gates and one 3-input NOR gate three 3-input OR gates and one 3-input AND gate None of these four input NAND gates only three 3-input NAND gates and one 3-input NOR gate ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics The XS-3 code is a error-correcting code self-complementing code weighted code cyclic code error-correcting code self-complementing code weighted code cyclic code ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Extremely low power dissipation per gate can be gained from MOS ICs ECL ICs CMOS ICs TTL ICs MOS ICs ECL ICs CMOS ICs TTL ICs ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Which of the following notations have two representations of zero? (I) 1’s complement with radix of number being 2 (II) 7’s complement with radix of number being 8 (III) 9’s complement with radix of number being 10 (IV) 10’s complement with radix of number being 10 Select the correct answer using the codes given below: (I) & (III) (I), (II) & (IV) (I), (II) & (III) (II), (III) & (IV) (I) & (III) (I), (II) & (IV) (I), (II) & (III) (II), (III) & (IV) ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is TTLAS TTLLS ECL CMOS TTLAS TTLLS ECL CMOS ANSWER DOWNLOAD EXAMIANS APP
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