Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. None of these Execution Unit (EU) Both ‘b’ and ‘c’ Bus Interface Unit (BIU) None of these Execution Unit (EU) Both ‘b’ and ‘c’ Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? TRAP both ‘a’ and ‘b’ RST 6.5 RST 5.5 TRAP both ‘a’ and ‘b’ RST 6.5 RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The clock speed of 8085 is 3.2KHz. 1MHz. 1KHz. 3.2MHz. 3.2KHz. 1MHz. 1KHz. 3.2MHz. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In one’s complement 8 bit representation 11111111 represents -1 -0 1 +0 -1 -0 1 +0 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Let the content of register C be 00000000 before the instruction DCR C is executed. The content of register C after the after the execution of this instruction will be 11111111 00000000 00000001 None 11111111 00000000 00000001 None ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The stack is nothing but a set of reserved I/O address space None of these reserved RAM address space reserved ROM address space reserved I/O address space None of these reserved RAM address space reserved ROM address space ANSWER DOWNLOAD EXAMIANS APP
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