Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Execution Unit (EU) Both ‘b’ and ‘c’ None of these Bus Interface Unit (BIU) Execution Unit (EU) Both ‘b’ and ‘c’ None of these Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor PSW stands for flag byte none accumulator and flag register contents accumulator contents flag byte none accumulator and flag register contents accumulator contents ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In microprocessor based system DMA refers to direct memory access for microprocessor direct memory access for the I/O device None of these direct memory access for the user direct memory access for microprocessor direct memory access for the I/O device None of these direct memory access for the user ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion (A): Each memory chip has its own address latch. Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip. A is wrong R is correct Both A and R are correct but R is not correct explanation of A A is correct R is wrong Both A and R are correct and R is correct explanation of A A is wrong R is correct Both A and R are correct but R is not correct explanation of A A is correct R is wrong Both A and R are correct and R is correct explanation of A ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction will never affect the zero flag? XRA R DCX Rp ORA R DCR R XRA R DCX Rp ORA R DCR R ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 P flag is reset when the result has even parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is set when the result has odd parity ANSWER DOWNLOAD EXAMIANS APP
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