Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During OPCODE fetch the state of S0 and S1 is 11 10 01 00 11 10 01 00 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following registers: 1. Accumulator and flag register 2. B and C register 3. D and E register 4. H and L register Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register? 2, 3 and 4 1, 2 and 3 1, 3 and 4 1, 2 and 4 2, 3 and 4 1, 2 and 3 1, 3 and 4 1, 2 and 4 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A good assembly language programmer should use general purpose registers rather than memory in maximum possible ways for data processing. This is because: Of limited set of instructions for data processing with memory Data processing with registers is easier than with memory Data processing with memory requires more instructions in the program than that with registers Data processing with registers takes fewer cycles than that with memory Of limited set of instructions for data processing with memory Data processing with registers is easier than with memory Data processing with memory requires more instructions in the program than that with registers Data processing with registers takes fewer cycles than that with memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 5.5 TRAP both ‘a’ and ‘b’ RST 6.5 RST 5.5 TRAP both ‘a’ and ‘b’ RST 6.5 ANSWER DOWNLOAD EXAMIANS APP
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