Microprocessor How many T-states are required for execution of OUT 80H instruction? 16 10 7 13 16 10 7 13 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following pair of gates can form a latch? A cross coupled NAND/OR A pair of cross copled AND A pair of cross coupled OR A pair of cross coupled NAND A cross coupled NAND/OR A pair of cross copled AND A pair of cross coupled OR A pair of cross coupled NAND ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operating modes of 8255 A are called Mode 0 and mode 2 Mode 0, mode 1 and mode 2 Mode 0, mode 2 and mode 3 Mode 0 and mode 1 Mode 0 and mode 2 Mode 0, mode 1 and mode 2 Mode 0, mode 2 and mode 3 Mode 0 and mode 1 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 P flag is set when the result has odd parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is reset when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is reset when the result has even parity ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T2 OP code fetch T1 OP code fetch T4 OP code fetch T3 OP code fetch T2 OP code fetch T1 OP code fetch T4 OP code fetch T3 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A microprocessor differentiates between op code, data/address at any time by the stack pointer its internal registers the sequence in which memory contents are fetched by it the program counter the stack pointer its internal registers the sequence in which memory contents are fetched by it the program counter ANSWER DOWNLOAD EXAMIANS APP
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