Digital Computer Electronics For an input pulse train of clock period T, the delay produced by an n stage shift register is (n-l)T (n+l)T 2nT nT None of these (n-l)T (n+l)T 2nT nT None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics When an inverter is placed between both inputs of an SR flip-flop, the resulting flip-flop is JK flip-flop T flip-flop Master slave JK flip-flop None of these D flip-flop JK flip-flop T flip-flop Master slave JK flip-flop None of these D flip-flop ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics What table shows the electrical state of a digital circuit's output for every possible combination of electrical states in the inputs? ASCII table Truth table None of these Function table Routing table ASCII table Truth table None of these Function table Routing table ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics The EXCLUSIVE - NOR gate is equivalent to an _____ gate followed by an invertor. None of these NAND OR XOR AND None of these NAND OR XOR AND ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics De Morgan's second therm says that NAND gate is equivalent to a bubbled _____ gate. None of these XOR OR AND XAND None of these XOR OR AND XAND ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics How many full and half-adders are required to add 16-bit numbers? None of these 8 half-adders, 8 full-adders 4 half-adders, 12 full-adders 16 half-adders, no full-adders 1 half-adders, 15 full-adders None of these 8 half-adders, 8 full-adders 4 half-adders, 12 full-adders 16 half-adders, no full-adders 1 half-adders, 15 full-adders ANSWER DOWNLOAD EXAMIANS APP
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