Digital Computer Electronics For an input pulse train of clock period T, the delay produced by an n stage shift register is nT (n+l)T None of these (n-l)T 2nT nT (n+l)T None of these (n-l)T 2nT ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics The time required for a pulse to decrease from 90 to 10 percent of its maximum value is known as None of these binary level transition period rise time decay time propagation delay None of these binary level transition period rise time decay time propagation delay ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics Conversion of binary number 1011012 to hexadecimal is None of these 3716 2D16 2716 20000000000000000 None of these 3716 2D16 2716 20000000000000000 ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics The 1's compliment of binary number 11010 is: 10 None of these 110 11101 101 10 None of these 110 11101 101 ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics An AND gate has 7 inputs. How many input word are in its truth table? 32 64 16 128 None of these 32 64 16 128 None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics Which of the following logic expression is wrong? 1 + 1 + 1 = 1 1+0+1 = 1 1 + 0=1 None of these 1 + 1=0 1 + 1 + 1 = 1 1+0+1 = 1 1 + 0=1 None of these 1 + 1=0 ANSWER DOWNLOAD EXAMIANS APP
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