Digital Computer Electronics For an input pulse train of clock period T, the delay produced by an n stage shift register is (n-l)T 2nT nT (n+l)T None of these (n-l)T 2nT nT (n+l)T None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics An odd-parity generator produces an odd-parity bit to go along with the data. The parity of the transmitted data is _____ An XOR gate can test each received word for parity rejecting words with _____ parity. None of these even, odd odd, even high, low low, high None of these even, odd odd, even high, low low, high ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics In which of the following adder circuits, the carry look ripple delay is eliminated? Carry-look-ahead adder Half adder None of these Full adder Parallel adder Carry-look-ahead adder Half adder None of these Full adder Parallel adder ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics The 1's compliment of binary number 11010 is: 10 101 110 None of these 11101 10 101 110 None of these 11101 ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics Conversion of an octal number 608 to binary number is 100112 1100002 11001112 11001102 None of these 100112 1100002 11001112 11001102 None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics How many outputs signals can a gate have? one None of these both (a) and (b) two only more than one one None of these both (a) and (b) two only more than one ANSWER DOWNLOAD EXAMIANS APP
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