Digital Computer Electronics For an input pulse train of clock period T, the delay produced by an n stage shift register is 2nT (n+l)T (n-l)T nT None of these 2nT (n+l)T (n-l)T nT None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics Addition of 11012 and 10102 is 101112 110112 None of these 101012 110002 101112 110112 None of these 101012 110002 ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics When the LOAD input of a buffer register is active, the input word is stored on the next positive _____ edge. None of these transistor pulse register clock None of these transistor pulse register clock ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics Which gates is known as universal gate? AND gate NOT gate XOR gate None of these NAND gate AND gate NOT gate XOR gate None of these NAND gate ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics The radix of the binary number is: 3 1 2 10 None of these 3 1 2 10 None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics A NOR gate has two or more input signals. All input must be _____ to get a high output low 1's None of these high some low some high low 1's None of these high some low some high ANSWER DOWNLOAD EXAMIANS APP
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