Digital Computer Electronics For an input pulse train of clock period T, the delay produced by an n stage shift register is 2nT None of these (n+l)T nT (n-l)T 2nT None of these (n+l)T nT (n-l)T ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics A NOR gate recognizes only the input word whose bits are _____ 0's 0's and 1's 0's or 1's 1's None of these 0's 0's and 1's 0's or 1's 1's None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics What is the ASCII code for T? 1011111 1010100 1011100 1011010 None of these 1011111 1010100 1011100 1011010 None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics Binary-Coded-decimal (BCD) numbers express each digit as a _____ None of these bit nibble All of these byte None of these bit nibble All of these byte ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics With a JK master-slave flip-flop the master is cocked when the clock is _____ and the slave is triggered when the clock is _____ None of these set, reset race, no change high, low set, race None of these set, reset race, no change high, low set, race ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics How many full and half-adders are required to add 16-bit numbers? 1 half-adders, 15 full-adders None of these 4 half-adders, 12 full-adders 16 half-adders, no full-adders 8 half-adders, 8 full-adders 1 half-adders, 15 full-adders None of these 4 half-adders, 12 full-adders 16 half-adders, no full-adders 8 half-adders, 8 full-adders ANSWER DOWNLOAD EXAMIANS APP
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