Microprocessor DS directive in 8085 Forces the assembler to reserve a specified number of consecutive bytes in the memory Forces the assembler to reserve one byte of memory None of these Forces the assembler to reserve a specified number of bytes in the memory Forces the assembler to reserve a specified number of consecutive bytes in the memory Forces the assembler to reserve one byte of memory None of these Forces the assembler to reserve a specified number of bytes in the memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Inintel 8085A microprocessor ALE signal is made high to To latch data D0-D7 from data bus To achieve all the functions listed above To disable data bus Enable the data bus to be used as low order address bus To latch data D0-D7 from data bus To achieve all the functions listed above To disable data bus Enable the data bus to be used as low order address bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following registers: 1. Accumulator and flag register 2. B and C register 3. D and E register 4. H and L register Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register? 2, 3 and 4 1, 2 and 4 1, 2 and 3 1, 3 and 4 2, 3 and 4 1, 2 and 4 1, 2 and 3 1, 3 and 4 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Internet is a worldwide network of computers where most of the information is freely available. False True False True ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Clears Complements Sets Can not change Clears Complements Sets Can not change ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the following? Instruction cycle Clock cycle Machine cycle Memory cycle Instruction cycle Clock cycle Machine cycle Memory cycle ANSWER DOWNLOAD EXAMIANS APP
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