Digital Computer Electronics Addition of 1101012 and 1011112 is 11101112 1100112 11001002 11010002 None of these 11101112 1100112 11001002 11010002 None of these ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics For an input pulse train of clock period T, the delay produced by an n stage shift register is (n+l)T nT 2nT None of these (n-l)T (n+l)T nT 2nT None of these (n-l)T ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics The 2's compliment of binary number 0.01011 is: None of these 1.101 0.101 1.10101 0.10101 None of these 1.101 0.101 1.10101 0.10101 ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics The m-bit parallel adder consists of: None of these m-1 full adders m full adders m/2 full adders (m+1) full adders None of these m-1 full adders m full adders m/2 full adders (m+1) full adders ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics Conversion of binary number 1011012 to hexadecimal is 20000000000000000 2716 2D16 None of these 3716 20000000000000000 2716 2D16 None of these 3716 ANSWER DOWNLOAD EXAMIANS APP
Digital Computer Electronics A combinational logic circuit which is used to send data coming from a single source to two or more separate destinations is called as demultiplexer multiplexer None of these encoder decoder demultiplexer multiplexer None of these encoder decoder ANSWER DOWNLOAD EXAMIANS APP
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