Digital Electronics The logic expression A + B can be implemented by giving inputs A and B to a two-input NAND gate X-OR gate NOR gate X-NOR gate NAND gate X-OR gate NOR gate X-NOR gate ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Which logic family provide minimum power dissipation ECL CMOS TTL JFET ECL CMOS TTL JFET ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics What is the minimum number of NOR gates required realizing an X-OR gating? 5 4 6 3 5 4 6 3 ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Which of the following gates is known as a coincidence detector? X-OR gate NAND gate AND gate X-NOR gate X-OR gate NAND gate AND gate X-NOR gate ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Dual slope ADC has R = 1 KΩ and C = 0.22 nanofarad has charging and discharge times for some voltage is 9 ns and 3 ns respectively. The reference Voltage is 2.2 V. What is the peak voltage reached by triangular wave during charging? 900 mV. 90 mV. 300 mV. 30 mV. 900 mV. 90 mV. 300 mV. 30 mV. ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics A gate is enabled when its enable input is at logic 1. The gate is NOR NAND OR none of these NOR NAND OR none of these ANSWER DOWNLOAD EXAMIANS APP
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