Digital Electronics A latch is ________ sensitive level both level and edge edge None level both level and edge edge None ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics The voltage levels for negative logic system must necessarily be negative must necessarily be 0 V and –5 V must necessarily be positive may be negative or positive must necessarily be negative must necessarily be 0 V and –5 V must necessarily be positive may be negative or positive ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics The output of a logic gate is 1 when all its inputs are at logic 0. The gate is either an AND or an X-NOR an X-OR or an X-NOR an OR or a NAND a NAND or a NOR an AND or an X-NOR an X-OR or an X-NOR an OR or a NAND a NAND or a NOR ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins? PLCC PGA QFP BGA PLCC PGA QFP BGA ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics What are the values of R1 and R2 respectively in the expression (235)R1 = (565)10 = (1065)R2 12, 8 6, 16 8, 16 16, 8 12, 8 6, 16 8, 16 16, 8 ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics If a counter having 10 flip flops is initially at 0, What count will if hold after 2060 pulses? 000 000 1110. 000 001 1100. 000 000 1000. 000 000 1100. 000 000 1110. 000 001 1100. 000 000 1000. 000 000 1100. ANSWER DOWNLOAD EXAMIANS APP
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